1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Background Art
When a CMOS (Complementary Metal-Oxide-Semiconductor) device in the submicron (0.1 μm) gate-length generation is manufactured, it is virtually impossible to use silicon (including an alloy with germanium, which will be referred to as “Si(Ge) gate” hereinafter), which has conventionally been used as a material of a gate electrode, in the same manner as before.
The first reason for this is that the resistivity of a Si(Ge) gate is high, i.e., a few hundreds μΩ·cm. When an actual layer thickness is 100 nm, the sheet resistance value becomes a few tens Ω/square. It is expected that in a semiconductor device of the submicron gate-length generation, an RC delay becomes evident with a resistivity of a gate electrode of 5 Ω/square or more, thereby curbing the high-speed operation of the device.
The second reason is the problem of Si(Ge) gate electrode depletion. This is a phenomenon in which a depletion layer having a limited length extends at the silicon gate electrode side of an interface between a silicon gate electrode and a gate dielectric film since the solubility limit of a dopant impurity added to silicon is about 1×1020 cm−3.
The depletion layer substantially serves as a capacitance connected in series to the gate dielectric film. Accordingly, this depletion capacitance, which is about 0.3 nm when converted to a silicon oxide layer, is added to the gate dielectric film. A gate dielectric film of a future generation is required to have a gate capacitance of 1.5 nm or less calculated as the thickness of a silicon oxide layer. The addition of a capacitance of 0.3 nm caused by the gate depletion is deemed to serve as a factor that would strictly limit the formation of a thinner gate dielectric film.
The third reason is a problem in that an impurity such as boron, which is added to decrease the resistance of the Si(Ge) gate, is thermally diffused into a silicon substrate through the gate dielectric film during a high temperature heat treatment step in the manufacturing of an LSI. Such impurity can be a factor for variance in the threshold voltage of the FET, thereby considerably degrading the electric characteristics of the device. Since an LSI in a future generation is required to have a far thinner gate dielectric film, the problem of thermal diffusion of an impurity added to a Si(Ge) gate to a silicon substrate is expected to become more serious in the future.
In order to solve the problems of Si(Ge) gates, high melting point metals such as molybdenum, tungsten, tantalum, etc., and nitrides thereof are used to form a gate electrode. This is known as metal gate technology.
The resistivity of a metal gate is lower than that of a Si(Ge) gate. Accordingly, the problem of the RC delay can be considerably alleviated. Furthermore, since the free-electron concentration within a metal gate is two or more orders higher than that of a Si(Ge) gate, and the width of the gate depletion is decreased by one or more orders, the added capacitance, which is 0.3 nm (calculated as that of a silicon oxide layer) in the case of a Si(Ge) gate, can be decreased to a level that can be ignored in the case of a metal gate. Moreover, since it is not necessary to add an impurity to a metal gate in order to decrease the resistance, there is no problem of impurity penetration through a gate dielectric film. Thus, a metal gate is expected to solve the problems of a Si(Ge) gate.
When a CMOS device including a metal gate is formed, the so-called dual phi (φ) metal gate technology is required, in which a metal material having a work function of p+ silicon, and a metal material having a work function of n+ silicon are used to form a p-channel MOSFET and an n-channel MOSFET, respectively. Using this technology, the threshold voltages of the p-channel MOSFET and the n-channel MOSFET can be completely controlled.
In the conventional art, TiN and TiAIN are proposed as a material for a metal gate of a p-channel MOSFET, and TaSiN is proposed as a material for a metal gate of an n-channel MOSFET (for example, D- G. Park, “IEDM”, Tech. Digest (2001) p. 671, and S. B. Samavedam, “VLSI”, Tech. Digest (2002) p. 24).
With such characteristics as having appropriate work functions, and being unmelted at a high temperature of about 900° C., thereby avoiding failures at an interface with a gate dielectric film, these materials are considered to be highly practical materials for forming a metal gate.
However, there are problems for these potentially practical materials. First, TiN and TiAIN are in a polycrystalline state. A gate electrode in a polycrystalline state would have the following problems.
The first problem is the mixing of an impurity into the lower part of a gate electrode during an ion implantation step. As a conventional way of manufacturing an LSI, ions are implanted to a processed gate electrode, thereby forming a source and a drain in a self-aligned manner with respect to the gate. However, when the gate electrode has a polycrystalline structure, accelerated ions pass through a grain boundary without scattering. Accordingly, the impurity is unintentionally introduced to a channel portion, thereby degrading characteristics of the device by varying the threshold voltage, etc.
The second problem is that since the grain size of the polycrystalline material forming the gate electrode is about the same as the device size, obviously a case may arise in which a gate electrode forming a single FET includes only a few crystal grains. In such a case, it is highly possible that variations in the number of crystal grains, the size thereof, and the crystal orientation thereof in the respective FETs may lead to variations in device characteristics.
On the other hand, TaSiN maintains an amorphous state even if it is subjected to high temperatures. This material can solve the aforementioned first and second problems involving polycrystalline material. However, there is a problem in that TaSiN in an amorphous state has extremely high resistivity. Generally, the resistance of a silicide can be decreased only when it is crystallized. Thus, the reason why the resistivity of TaSiN is high is this material is in an amorphous state.
As described above, a conventional Si(Ge) gate has such problems as a high resistivity leading to an RC delay, thereby curbing the high-speed operation of the device, the depletion of a Si(Ge) gate electrode leading to a loss of gate dielectric film capacitance, and the thresholds voltage varying due to the penetration of an impurity from the silicon gate electrode into the gate dielectric film.
Metal gate materials conventionally used to solve the aforementioned problems also have a dilemma in that ion penetration occurs with a low resistance material which is in a polycrystalline state, thereby varying the device characteristics, while an amorphous material cannot decrease the resistivity.